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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
DDR SDRAM DIMM
Features
* JEDEC-standard 184-pin dual in-line memory module (DIMM) * Fast data transfer rates PC1600, PC2100, or PC2700 * Utilizes 200 MT/s, 266 MT/s, and 333MT/s DDR SDRAM components * ECC-optimized pinout 128MB (16 Meg x 72), 256MB (32 Meg x 72) * VDD= VDDQ= +2.5V * VDDSPD = +2.3V to +3.6V * +2.5V I/O (SSTL_2 compatible) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle * Bidirectional data strobe (DQS) transmitted/ received with data--i.e., source-synchronous data capture * Differential clock inputs (CK and CK#) * Four internal device banks for concurrent operation * Programmable burst lengths: 2, 4, or 8 * Auto precharge option * Auto Refresh and Self Refresh Modes * 15.6s (128MB), 7.8125s (256MB) maximum average periodic refresh interval * Serial Presence-Detect (SPD) with EEPROM * Programmable READ CAS latency
MT9VDDT1672A - 128MB MT9VDDT3272A - 256MB
For the latest data sheet, please refer to the Microna Web site: www.micron.com/moduleds
Figure 1: 184-Pin DIMM (MO-206)
OPTIONS * Package Unbuffered 184-pin DIMM (Gold) 184-pin DIMM (Lead-Free) * Frequency/CAS Latency 6ns, 333 MT/s (167 MHz), CL = 2.5 7.5ns, 266 MT/s (133 MHz ), CL = 2 7.5ns, 266 MT/s (133 MHz ), CL = 2 7.5ns, 266 MT/s (133 MHz ), CL = 2.5 10ns, 200 MT/s (100 MHz ), CL = 2 * Self Refresh Standard Low Power
MARKING A G Y -335 -262 -26A -265 -202 None L
Table 1:
Address Table
128MB 256MB 8K 8K (A0-A12) 4 (BA0, BA1) 32 Meg x 8 1K (A0-A9) 1 (S0#)
4K Refresh Count 4K (A0-A11) Row Addressing Device Bank Addressing 4 (BA0, BA1) 16 Meg x 8 Device Configuration 1K (A0-A9) Column Addressing 1 (S0#) Module Rank Addressing
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(c)2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 2: Part Numbers and Timing Parameters
MODULE DENSITY 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB CONFIGURATION 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 MODULE BANDWIDTH 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s MEMORY CLOCK/ DATA RATE 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s LATENCY (CL - tRCD - tRP) 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2
PART NUMBER MT9VDDT1672A(L)G-335__ MT9VDDT1672A(L)Y-335__ MT9VDDT1672A(L)G-262__ MT9VDDT1672A(L)Y-262__ MT9VDDT1672A(L)G-26A__ MT9VDDT1672A(L)Y-26A__ MT9VDDT1672A(L)G-265__ MT9VDDT1672A(L)Y-265__ MT9VDDT1672A(L)G-202__ MT9VDDT1672A(L)Y-202__ MT9VDDT3272A(L)G-335__ MT9VDDT3272A(L)Y335__ MT9VDDT3272A(L)G-262__ MT9VDDT3272A(L)Y-262__ MT9VDDT3272A(L)G-26A__ MT9VDDT3272A(L)Y-26A__ MT9VDDT3272A(L)G-265__ MT9VDDT3272A(L)Y-265__ MT9VDDT3272A(L)G-202__ MT9VDDT3272A(L)Y-202__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT3272AG-265A1
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 3: Pin Assignment (184-Pin DIMM Front)
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDD DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDD DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDD WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS CK2# CK2 VDD DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
Table 4:
Pin Assignment (184-Pin DIMM Back)
116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDD DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDD CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 VSS DQS17 A10 CB6 VDD CB7 VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44 RAS# DQ45 VDD S0# NC DQS14 VSS DQ46 162 DQ47 163 NC 164 VDD 165 DQ52 166 DQ53 167 NC 168 VDD 169 DQS15 170 DQ54 171 DQ55 172 VDD 173 NC 174 DQ60 175 DQ61 176 VSS 177 DQS16 178 DQ62 179 DQ63 180 VDD 181 SA0 182 SA1 183 SA2 184 VDDSPD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 93 VSS 94 DQ4 95 DQ5 96 VDD 97 DQS9 98 DQ6 99 DQ7 100 VSS 101 NC 102 NC 103 NC 104 VDD 105 DQ12 106 DQ13 107 DQS10 108 VDD 109 DQ14 110 DQ15 111 NC 112 VDD 113 NC 114 DQ20 115 NC/A12
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDD CK1 CK1# VSS DQ10 DQ11 CKE0 VDD DQ16
Pin 115 is No Connect (128MB), and A12 (256MB).
Figure 2: 184-Pin DIMM Pinouts
FRONT VIEW
U10
U1
U2
U3
U4
U5
U6
U7
U8
U9
PIN 1
PIN 52 Indicates a VDD pin
PIN 53 Indicates a VSS pin
PIN 92
BACK VIEW
No Components This Side
PIN 184
PIN 145
PIN 144
PIN 93
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 5: Pin Descriptions
SYMBOL VREF WE#, CAS#, RAS# CK0, CK0#, CK1, CK1#, CK2, CK2# TYPE Input Input Input DESCRIPTION SSTL_2 reference voltage. Command Inputs: WE#, RAS#, and CAS# (along with S#) define the command being entered. Clocks: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE activates (HIGH) and deactivates (LOW) internal clock signals, device input buffers, and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE0 is synchronous for all functions except for disabling outputs, which is achieved asynchronously. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Chip Select: S# enables (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Bank Addresses: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: Sampled during the ACTIVE command (row-address) and READ/WRITE command (columnaddress, with A10 defining auto precharge) to select one location out of the memory array in the respective device device bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one device bank (A10 LOW) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. Data I/Os: Check bits. ECC, one-bit error detection and correction. Data Strobes: Output with read data, input with write data. Edge- aligned with read data, centered in write data. Used to capture write data. Refer to Pin Assignment Tables on page 3 for pin number and symbol information PIN NUMBERS 1 63, 65, 154 16, 17, 75, 76, 137, 138
21
CKE0
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48, 115 (256MB), 118, 122, 125, 130, 141
A0-A11 (128MB) A0-A12 (256MB)
Input
92
SCL
Input
181, 182, 183 91
SA0-SA2 SDA
Input Input/Output
44, 45, 49, 51, 134, 135, 142, 144 5, 14, 25, 36, 47, 56, 67, 78, 86, 97, 107, 119, 129, 140, 149, 159, 169, 177
CB0-CB7 DQS0-DQS17
Input/Output Input/Output
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 5: Pin Descriptions (Continued)
DQ0-DQ63 Input/Output Data I/Os: Data bus. Refer to Pin Assignment Tables on page 3 for pin number and symbol information 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 117, 121, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 7, 15, 22, 30, 38, 46, 54, 62, 70, 77, 85, 96, 104, 108, 112, 120, 128, 136, 143, 148, 156, 164, 168, 172, 180 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 9, 10, 71, 82, 90, 101, 102, 103, 111, 113, 115 (128MB), 158, 163, 167, 173
VDD
Supply
Power Supply: +2.5V +0.2V. (Please see note 50 on page 21.)
VSS
Supply
Ground.
VDDSPD NC
Supply -
Serial EEPROM positive power supply: +2.3V to +3.6V. This supply is isolated from the VDD/VDDQ supply. No Connects.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Figure 3: Functional Block Diagram -26A, -265, -202 Speed Optimized
S0# DQS0 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0, BA1 A0-A11 (128MB) A0-A12 (256MB) RAS# CAS# WE# CKE0 DM CS# DQS DQ DQ DQ U5 DQ DQ DQ DQ DQ BA0, BA1: SDRAMs A0-A11: SDRAMs A0-A12: SDRAMs RAS#: SDRAMs CAS#: SDRAMs WE#: SDRAMs CKE0: SDRAMs SA0 SA1 SA2 SCL WP CK0 CK0#
4.5pF
DQS4 DQS13 DM CS# DQS DQ DQ DQ DQ U1 DQ DQ DQ DQ DQS5 DQS14 DM CS# DQS DQ DQ DQ U2 DQ DQ DQ DQ DQ DQS6 DQS15 DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DQS7 DQS16 DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ 120 SDRAM X3 120 CK2 CK2#
4.5pF
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DM CS# DQS DQ DQ DQ U6 DQ DQ DQ DQ DQ
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM CS# DQS DQ DQ DQ DQ U7 DQ DQ DQ DQ
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM CS# DQS DQ DQ DQ U8 DQ DQ DQ DQ DQ
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM CS# DQS DQ DQ DQ U9 DQ DQ DQ DQ DQ 120 CK1 CK1#
4.5pF
SDRAM X3
SDRAM X3
VDDSPD VDDQ VDD VREF VSS
SPD/EEPROM SDRAMs SDRAMs SDRAMs SDRAMs SERIAL PD
U10
A0 A1 A2
SDA
NOTE:
1. 2. All resistor values are 22W unless otherwise specified. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide.
U1 - U9 = MT46V16M8TG DDR SDRAMs 128MB Module U1 - U9 = MT46V32M8TG DDR SDRAMs 256MB Module
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Figure 4: Functional Block Diagram -335 Speed Optimized
S0# DQS0 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0, BA1 A0-A11 (128MB) A0-A12 (256MB) RAS# CAS# WE# CKE0
5.1 5.1 5.1 5.1 5.1 5.1
DQS4 DQS13 DM CS# DQS DQ DQ DQ DQ U1 DQ DQ DQ DQ DQS5 DQS14 DM CS# DQS DQ DQ DQ U2 DQ DQ DQ DQ DQ DQS6 DQS15 DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DQS7 DQS16 DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ 120 DM CS# DQS DQ DQ DQ U9 DQ DQ DQ DQ DQ BA0, BA1: SDRAMs A0-A11: SDRAMs A0-A12: SDRAMs RAS#: SDRAMs CAS#: SDRAMs WE#: SDRAMs CKE0: SDRAMs SA0 SA1 SA2 SCL WP CK0 CK0#
3pF
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DM CS# DQS DQ DQ DQ U5 DQ DQ DQ DQ DQ
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM CS# DQS DQ DQ DQ DQ U6 DQ DQ DQ DQ
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM CS# DQS DQ DQ DQ U8 DQ DQ DQ DQ DQ 120
SDRAM X3 120 CK2 CK2#
3pF
CK1 CK1#
3pF
SDRAM X3
SDRAM X3
VDDSPD VDDQ VDD VREF VSS
SPD/EEPROM SDRAMs SDRAMs SDRAMs SDRAMs SERIAL PD
U10
A0 A1 A2
SDA
NOTE:
1. 2. All resistor values are 22W unless otherwise specified. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide.
U1 - U9 = MT46V16M8TG DDR SDRAMs 128MB Module U1 - U9 = MT46V32M8TG DDR SDRAMs 256MB Module
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
General Description
The MT9VDDT1672A and MT9VDDT3272A are high-speed CMOS, dynamic random-access, 128MB and 256MB memory modules organized in a x72 (ECC) configuration. These modules use internally configured quad-bank DDR SDRAM devices. These DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, oneclock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clockcycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. These DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select device bank; A0-A11 select device row for the 128MB module, A0-A12 select device row for the 256MB module). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. These DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAM modules, the pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb and 256Mb DDR SDRAM component data sheet.
Serial Presence-Detect Operation
These DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/ WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect.
Mode Register Definition
The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 5, Mode Register Definition Diagram, on page 9. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 (for the 128MB module) or A7-A12 (for the 256MB module) specify the operating mode.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A9 when the burst length is set to two, by A2-A9 when the burst length is set to four and by A3-A9 when the burst length is set to eight (where A9 is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts.
Figure 5: Mode Register Definition Diagram
128MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 0* 0*
8 6 5 4 10 11 10 9 7 3 2 Operating Mode CAS Latency BT Burst Length
Mode Register (Mx)
* M13 and M12 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register).
256MB Module
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 Operating Mode 0* 0* * M14 and M13 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register).
7
6 5 4 10 3 2 CAS Latency BT Burst Length
Mode Register (Mx)
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 M3 0 1 M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M6-M0 Valid Valid 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved M3 = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page 10.
0 0 0 0 0 -
M12 M11 M10 M9 M8 M7 0 0 0 1 0 0 -
Read Latency
The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS Latency Diagram, on page 10. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency (CL) Table, on page 10, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
0 -
Operating Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 (128MB), or A7-A12 (256MB) each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 (128MB), or A7 and A9-A12 (256MB) each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A11, or A7- A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
Figure 6: CAS Latency Diagram
T0 CK# CK COMMAND
READ NOP NOP NOP
T1
T2
T2n
T3
T3n
CL = 2 DQS
Table 6:
Burst Definition Table
ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 TYPE = INTERLEAVED 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
DQ T0 T1 T2 T2n T3 T3n
CK# CK COMMAND
STARTING BURST COLUMN LENGTH ADDRESS 2 A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
READ
NOP
NOP
NOP
CL = 2.5 DQS DQ
4
Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA DON'T CARE
8
Table 7:
CAS Latency (CL) Table
ALLOWABLE OPERATING FREQUENCY (MHZ)
SPEED -335 -26A -265 -202
CL = 2 N/A 75 f 133 75 f 100 75 f 100
CL = 2.5 75 f 167 75 f 133 75 f 133 75 f 125
NOTE:
1. For a burst length of two, A1-Ai select the twodata-element block; A0 selects the first access within the block. 2. or a burst length of four, A2-Ai select the fourdata-element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eightdata-element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 11 for 128MB module, i = 12 for 256MB module
Extended Mode Register
The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 7, Extended Mode Register Definition Diagram, on page 11. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both low) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
Figure 7: Extended Mode Register Definition Diagram
128MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 01 11
9
876 54 Operating Mode
3
22
1
0
DS DLL
Extended Mode Register (Ex)
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
256MB Module
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
876 5 14 13 12 11 10 9 Operating Mode 01 11
4
3
22
1
0
DS DLL
Extended Mode Register (Ex)
E0 0 1 E1 0 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - E1, E0 Valid -
DLL Enable Disable Drive Strength Normal
Operating Mode Reserved Reserved
NOTE:
1. E13 and E12 (128MB module), or E14 and E13 (256MB Module) (BA1 and BA0) must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported.
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Commands
The Truth Tables below provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 128Mb and 256Mb DDR SDRAM component data sheets.
Table 8:
Notes: 1
Truth Table - Commands
NAME (FUNCTION) CS# H L L L L L L L L RAS# CAS# X H L H H H L L L X H H L L H H L L WE# X H H H L L L H L ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code NOTES 2 2 3 4 4 5 6 7, 8 9
DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER
NOTE:
1. 2. 3. 4. 5. 6. 7. 8. 9.
CKE is HIGH for all commands shown except SELF REFRESH. DESELECT and NOP are functionally interchangeable. BA0-BA1 provide device bank address and A0-A11 (128MB) or A0-A12 (256MB) provide device row address. BA0-BA1 provide device bank address; A0-A9 provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls device row addressing; all inputs and I/Os are "Don't Care" except for CKE. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 (for 128MB module) or A0-A12 (for 256MB module) provide the op-code to be written to the selected mode register.
Table 9:
Truth Table - DM Operation
NAME (FUNCTION) DM L H DQS Valid X
Used to mask write data; provided coincident with the corresponding data
WRITE Enable WRITE Inhibit
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operaVoltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VDDQ Supply Relative to VsSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V
Notes: 1-5, 14, 50; notes appear on pages 18-21; 0C TA +70C PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT: Any input 0V VIN VDD, VREF pin 0V VIN 1.35V (All other pins not under test = 0V) SYMBOL VDDQ VDDQ VREF VTT VIH(DC) VIL(AC) IL MIN MAX UNITS V V V V V V A NOTES 32, 36 32, 36, 39 6, 39 7, 39 25 25 49
tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Temperature, TA (ambient) . . . . . . . . . . . . . . . . . . . . . .0C to +70C Storage Temperature (plastic) . . . . . . -55C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9W Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA
Table 10: DC Electrical Characteristics and Operating Conditions
OUTPUT LEAKAGE CURRENT: (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
Command/Address, RAS#, CAS#, WE#, CKE, S# CK, CK# DM DQ, DQS
2.3 2.7 2.3 2.7 0.49 x VDDQ 0.51 x VDDQ VREF - 0.04 VREF + 0.04 VREF + 0.15 VDD + 0.3 -0.3 VREF - 0.15 -18 18
IL IL IOZ IOH IOL
-6 -2 -5 -16.8 16.8
6 2 5 - -
A A A mA mA
49 49 49 33, 36 34
Table 11: AC Input Operating Conditions
Notes: 1-5, 12, 14, 50; notes appear on pages 18-21; 0C TA +70C; VDD = VDDQ = +2.5V +0.2V PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage SYMBOL VIH(AC) VIL(AC) VREF(AC) MIN VREF + 0.310 - 0.49 x VDDQ MAX - VREF - 0.310 0.51 x VDDQ UNITS V V V NOTES 25, 35 25, 35 6
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 12: IDD Specifications and Conditions (128MB)
DRAM components only Notes: 1-5, 8, 10, 12, 50; notes appear on pages 18-21; 0C TA +70C; VDD = VDDQ = +2.5V +0.2V MAX PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One device bank; Active-ReadPrecharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t AUTO REFRESH CURRENT RC = tRFC (MIN) RC = 15.625s Standard Low Power OPERATING CURRENT: Four device bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands. SELF REFRESH CURRENT: CKE 0.2V
t
SYMBOL IDD0
-335 TBD
-262 TBD
-26A/ -265 945
-202 900
UNITS mA
NOTES 20, 43
IDD1
TBD
TBD
1,080
990
mA
20, 43
IDD2P IDD2F
TBD TBD
TBD TBD
27 405
27 315
mA mA
21, 28, 45 46
IDD3P IDD3N
TBD TBD
TBD TBD
180 405
180 315
mA mA
21, 28, 45 40
IDD4R
TBD
TBD
1,125
945
mA
20, 43, 24, 45 20
IDD4W
TBD
TBD
1,035
945
mA
IDD5 IDD5A IDD6 IDD6A IDD7
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
1,890 45 18 9 2,925
1,845 45 18 9 2,475
mA mA mA mA mA
24, 45 24, 45 9 20, 44
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 13: IDD Specifications and Conditions (256MB)
DRAM components only Notes: 1-5, 8, 10, 12, 50; notes appear on pages 18-21; 0C TA +70C; VDD = VDDQ = +2.5V +0.2V MAX PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One device bank; Active-ReadPrecharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t AUTO REFRESH CURRENT RC = tRFC (MIN) RC = 7.8125s SELF REFRESH CURRENT: CKE 0.2V Standard Low Power OPERATING CURRENT: Four device bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands.
t
SYMBOL IDD0
-335 1,125
-262 1,125
-26A/ -265 945
-202 1,080
UNIT S mA
NOTES 20, 43
IDD1
1,530
1,440
1,305
1,395
mA
20, 43
IDD2P IDD2F
36 450
36 405
36 405
36 405
mA mA
21, 28, 45 46
IDD3P
270
225
225
270
mA
21, 28, 45 42
IDD3N
540
450
450
450
mA
IDD4R
1,575
1,350
1,350
1,575
mA
20, 43, 24, 45 20
IDD4W
1,395
1,215
1,215
1,710
mA
IDD5 IDD6 IDD7 IDD7A IDD8
2,295 54 36 18 3,645
2,115 54 36 18 3,150
2,115 54 36 18 3,285
2,205 54 36 18 3,285
mA mA mA mA mA
24, 45 24, 45 9 20, 44
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 14: Capacitance (All Modules)
Note: 11; notes appear on pages 18-21 PARAMETER Input/Output Capacitance: DQs, DQSs Input Capacitance: Command and Address, S0# Input Capacitance: CK0, CK0# (-26A, -265, -202) Input Capacitance: CK0, CK0# (-335) Input Capacitance: CK1, CK1#, CK2, CK2# (-26A, -265, -202) Input Capacitance: CKE SYMBOL CIO CI1 CI2 CI2 CI2 CI3 MIN 4.0 2.0 12.0 9 10.5 18.0 MAX 5.0 3.0 15.0 12.0 13.5 27.0 UNITS pF pF pF pF pF pF
Table 15: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 1-5, 8, 12-15, 29, 31, 50; notes appear on pages 18-21; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS PARAMETER Access window of DQ from CK/CK# CK high-level width CK low-level width Clock cycle time CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor
t t t t
-335 SYMBOL
t t
-26A/265
-202 MIN -0.8 0.45 0.45 8 10 0.6 0.6 2 -0.8 0.35 0.35 +0.8 MAX UNITS NOTES +0.8 0.55 0.55 13 13 ns
t t
MIN -0.7 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35
MAX MIN MAX +0.7 0.55 0.55 13 13 -0.75 +0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 +0.60 -0.75 +0.75 0.35 0.35 0.45 0.5 0.75 0.2 0.2
t t t
AC CH CL
0.55 0.55 13 13
CK
26 26 40, 47, 48 40, 47 23, 27 23, 27 27
t
CK (2.5)
t
CK ns
CK (2)
t
ns ns ns ns ns
t t
DH DS
t
DIPW
DQSCK DQSH DQSL
t
t
CK 22, 25
t
DQSQ DQSS
t t
0.6 0.75 0.2 0.2
t t
CK ns CK CK
t
0.75 0.2 0.2
t
1.25
1.25
1.25
t t t
DSS HP HZ LZ
DSH
t t
CH, CL +0.70
CH, CL +0.75
CH, CL +0.8
CK ns ns ns ns ns ns ns
30 16, 37 16, 38 12 12 12 12
t t
-0.70 0.75 0.75 0.80 0.80 12
t
-0.75 0.90 0.90 1 1 15
t t
-0.8 1.1 1.1 1.1 1.1 16
t t
IHF ISF
t t
IHS ISS
t
MRD
t
ns
t
QH
HP - QHS 0.55
HP - QHS 0.75
HP- QHS 1
ns ns
22, 23
t
QHS
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 15: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
AC CHARACTERISTICS PARAMETER ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to READ with Auto precharge command 128MB 256MB SYMBOL
t t
-335 MIN 42
-26A/265
-202 MIN 40 MAX UNITS NOTES 120,000 ns ns ns ns ns ns ns 1.1 0.6
t t
MAX MIN MAX 70,000
t
RAS
40
120,000
31 40
RAP RAP
t
RAS(MIN) - (burst length) * t CK/2) RAS(MIN) - (burst length) * t CK/2) 65 70 75 20 20 80 20 20 1.1 0.6 0.9 0.4 15 0.25 0 0.6 0.4 15 1
t t t
t
18 60 72 18 18 0.9 0.4 12 0.25 0 0.4 15 1
t t
t
ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval REFRESH to REFRESH command interval Average periodic refresh interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 128MB 256MB 128MB 256MB
t t t t t t t
RC
t
RFC RP
45
RCD
t
RPRE RPST RRD
1.1 0.6
0.9 0.4 15 0.25 0
CK
37
t
CK ns CK ns 18, 19 17
WPRE WPST
t
t
WPRES WR
t
0.6
0.4 15 1
t
0.6
t
CK ns CK ns
t
WTR na
t
REFC REFC REFI REFI
QH - DQSQ 140.6 70.3 15.6 7.8 0 75
QH - DQSQ 140.6 140.6 15.6 7.8 0 75
QH - DQSQ 140.6 140.6 15.6
22 21 21 21 21
s s s s ns ns
t
t t
tVTD t t
XSNR XSRD
200
200
CK
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Notes
1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load:
VTT 50 Reference Point 30pF
12.
Output (VOUT)
13. 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for -265 and -335 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA =
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
14.
15. 16.
17.
18.
19.
20.
21.
25C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. Command/Address input slew rate = 0.5V/ns. For -335 and -262, -26A, and -265 with slew rates 1V/ ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for Idd measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period 64ms. This equates to an average refresh rate of 15.625s (128MB module) 7.8125s (256MB module). However, an AUTO REFRESH command must be asserted at least
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
18
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
once every 140.6s (128MB module) or 70.3s (256MB module); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and t QH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. Figure 8, Derating Data Valid Window (tQH - tDQSQ), shows the derating curves for duty cycles ranging between 50/50 and 45/55. Each byte lane has a separate DQS, with DQ0- DQ7. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). To maintain a valid level, the transitioning edge of the input must: a)Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b)Reach at least the target AC level. c)After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). CK and CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially). DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and t DH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. VDD must not vary more than 4 percent if CKE is not active while any device bank is active. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. t HP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active.
22.
26. 27.
23. 24.
28. 29.
30.
25.
Figure 8: Derating Data Valid Window (tQH - tDQSQ)
3.8 3.750 3.6 3.400 3.4 3.700
3.650
3.600
3.550 3.500 3.450 3.400 3.200 3.150 3.100 3.350 3.300
3.350
3.300 3.250
3.2 -26A/-265 @ tCK = 10ns -202 @ tCK = 10ns -26A/-265 @ tCK = 7.5ns -202 @ tCK = 8ns TBD -335 @ tCK = 6ns
3.250
3.050 3.000 2.950 2.900
3.0 ns 2.8 2.6
2.500
2.463
2.425
2.388
2.4
2.350
2.313
2.275
2.238
2.200
2.163
2.2
2.125
2.0
1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 Clock Duty Cycle 47/53 46.5/54.5 46/54 45.5/55.5 45/55
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either 300mV or 2.2V, whichever is more positive. The DC average cannot go below 2.3V minimum. 33. Normal Output Drive Curves: a)The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. b)The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. c)The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. e)The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f ) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. The voltage levels used are derived from a minimum VDD level and the refernced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VDD and VDDQ must track each other. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ (MAX) and the last DVW. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over t DQSCK (MIN) + tRPRE (MAX) condition. For slew rates of greater than 1V/ns the (LZ) transition will start about 310ps earlier. During initialzation, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0.0V, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin.
34.
35.
36. 37.
38. 39.
Figure 9: Pull-Down Characteristics
160 140 120 100
0
Figure 10: Pull-Up Characteristics
Maxim
um
-20 -40 -60
Maximum
Nominal high
high Nominal
IOUT (mA)
IOUT (mA)
-80 -100 -120 -140 -160 -180 -200
80
Nominal low
60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5
Nom
inal
low
Minimum
Min
imu
m
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
VDDQ - VOUT (V)
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
40. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. tRAP tRCD. 42. For -335, -262, -26A, and -265 speed grades, IDD3N is specified to be 35mA x (# of DDR SDRAM devices) at 100 MHz. 43. Random addressing changing and 50 percent of data changing at every transfer. 44. Random addressing changing and 100 percent of data changing at every transfer. 45. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 46. IDD2N specifies the DQ, DQS and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 47. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 48. Min tCK value at CL=2.5 in the SPD for and -26A speeds is 0.7ns, to facilitate proper system operation. 49. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 50. The -335 module speed grade, using the -6R speed device, has VDD (MIN) = 2.4V.
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
SPD Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure 12, Definition of Start and Stop).
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 12, Definition of Start and Stop). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode.
Figure 11: Data Validity
Figure 12: Definition of Start and Stop
SCL
SCL
SDA
DATA STABLE DATA CHANGE DATA STABLE
SDA
START BIT
STOP BIT
Figure 13: Acknowledge Response from Receiver
SCL from Master
8
9
Data Output from Transmitter
Data Output from Receiver Acknowledge
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 16: EEPROM Device Select Code
Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER b7 1 0 b6 0 1 b5 1 1 b4 0 0 CHIP ENABLE b3 SA2 SA2 b2 SA1 SA1 b1 SA0 SA0 RW b0 RW RW
Table 17: EEPROM Operating Modes
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write RW BIT 1 0 1 1 0 0 WC VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL BYTES 1 1 1 1 1 16 INITIAL SEQUENCE START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1' Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0'
Figure 14: SPD EEPROM Timing Diagram
tF t LOW t HIGH tR
SCL
t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO
SDA IN
t AA t DH t BUF
SDA OUT
UNDEFINED
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VREF POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz SYMBOL VDD VIH VIL VOL ILI ILO ISB ICC MIN MAX UNITS V V V V A A A mA
3 3.6 VDD x 0.7 VDD + 0.5 -1 VDD x 0.3 - 0.4 - 10 - 10 - 30 - 2
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
t t t t t t t
SYMBOL
t t
MIN 0.3 4.7 300
MAX 3.5
UNITS s s ns
NOTES
AA DH
t
BUF F
t
300 0 4 4 100 4.7 1 100 250 4.7 4.7 10
ns s s s ns s s KHz ns s s ms 1
HD:DAT HD:STA
t
HIGH
t
I
LOW
t
R
SCL
SU:DAT SU:STA
t
SU:STO WRC
1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 20: Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes at end of SPD Matrix BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION Number of Bytes Used by Micron Total Number of SPD Memory Bytes Memory Type Number of Row Addresses Number of Column Addresses Number of Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, tCK, (CAS Latency = 2.5) (See note 1) ENTRY (VERSION) 128 256 SDRAM DDR 12 or 13 10 1 72 0 SSTL 2.5V 6ns (-335) 7ns (-262/-26A) 7.5ns (-265) 8ns (-202) 0.7ns (-335) 0.75ns (-262/-265/-26A) 0.8ns (-202) ECC 15.6 or 7.81s/SELF 8 8 1 2, 4, 8 4 2, 2.5 0 1 Unbuffered, Diff CLK Fast/concurrent auto precharge 7.5ns (-335/-262/-26A) 10ns (-202/-265) 0.7ns (-335) 0.75ns (-262/-265/-26A) 0.8ns (-202) - - 18ns (-335) 20ns (-262) 20ns (-202/-265/-26A) 12ns (-335) 15ns (-202/-265/-26A)/-262 18ns (-335) 20ns (-262) 20ns (-202/-265/-26A) MT9VDDT1672A 80 08 07 0C 0A 01 48 00 04 60 70 75 80 70 75 80 02 80 08 08 01 0E 04 0C 01 02 20 00/C0 (See note 2) 75 A0 70 75 80 00 00 48 3C 50 30 3C 48 3C 50 MT9VDDT3272A 80 08 07 0D 0A 01 48 00 04 60 70 75 80 70 75 80 02 82 08 08 01 0E 04 0C 01 02 20 C0 75 A0 70 75 80 00 00 48 3C 50 30 3C 48 3C 50
10
SDRAM Access From Clock, tAC (CAS Latency = 2.5) Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-Checking SDRAM Data Width Minimum Clock Delay, Back -to- Back Random Column Access Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, tCK (CAS Latency = 2) SDRAM Cycle Time, tCK (CAS Latency = 2) (See note 1) SDRAM Cycle Time, tCK (CAS Latency = 1) SDRAM Access From CK , (CAS latency = 1) Minimum Row Precharge Time, RP
t
11 12 13 14 15 16 17 18 19 20 21 22 23 24
25 26 27
28 29
Minimum Row Active To Row Active, tRRD Minimum RAS# to CAS# Delay, tRCD
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
25
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 20: Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes at end of SPD Matrix BYTE 30 DESCRIPTION Minimum RAS# Pulse Width, tRAS ENTRY (VERSION) 42ns (-335) 45ns (-262/-265/-26A) 40ns (-202) 128MB or 256MB 0.8ns (-335) 1.0ns (-262/-265/-26A) 1.1ns (-202) 0.8ns (-335) 1.0ns (-262/-265/-26A) 1.1ns (-202) 0.45ns (-335 0.5ns (-262/-265/-26A) 0.6ns (-202) 0.45ns (-335 0.5ns (-262/-265/-26A) 0.6ns (-202) MT9VDDT1672A MT9VDDT3272A 2A 2D 28 40 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 60 75 A0 00 00 33 B7 E8 18 B3 2C 00 01-0B Variable Data 01-09 00 Variable Data
31 32
33
34
35
36-40 41
42
43 44
45
46-61 62 63
64 65-71 72 73-90 91 92 93
2A 2D 28 20 Module Rank Density 80 Address and Command Setup Time, tIS A0 (See note 3) B0 t 80 Address and Command Hold Time, IH A0 (See note 3) B0 45 Data/Data Mask Input Setup Time, tDS 50 60 t 45 Data/Data Mask Input Hold Time, DH 50 60 00 Reserved t 60ns (-335/-262) 3C Minimum Active/Auto Refresh Time, ( RC) 65ns (-265/-26A) 41 70ns (-202) 46 72ns (-335) 48 Minimum Auto Refresh to Active/ Auto 75ns (-262/-265/-26A) 4B Refresh Command Period, (tRFC) 80ns (-202) 50 t 30 12ns (-335) Maximum Cycle Time, ( CK (MAX)) 13ns (-202/-265/-26A/-262) 34 t 0.45ns (-335) 2D Maximum DQS-DQ Skew Time, ( DQSQ) 0.5ns (-262-265/-26A) 32 0.6ns (-202) 3C 0.6ns (-335) 60 Maximum Read Data Hold Skew Factor, (tQHS) 0.75ns (-262/-265/-26A) 75 1ns (-202) A0 00 Reserved Release 0.0 00 SPD Revision -335 na/10 (See note 2) Checksum for Bytes 0-62 -262 94 -26A 05/C5 (See note 2) -265 35/F5 (See note 2) -202 D0/90 (See note 2) MICRON 2C Manufacturer's JEDEC ID Code 00 Manufacturer's JEDEC ID Code (Continued) 01-11 01-0B Manufacturing Location Variable Data Module Part Number (ASCII) 1-9 01-09 PCB Identification Code 0 00 Identification Code (Continued) Variable Data Year of Manufacture in BCD
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
26
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Table 20: Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes at end of SPD Matrix BYTE 94 95-98 99-127
NOTE:
DESCRIPTION Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD)
ENTRY (VERSION)
MT9VDDT1672A Variable Data Variable Data -
MT9VDDT3272A Variable Data Variable Data -
1. The value of tCK for -26A modules is set at 7.0ns. Component spec. value is 7.5ns. 2. Supports Fast/Concurrent Auto Precharge. Values are listed in the form "without Concurrent Auto Precharge" / "with Concurrent Auto Precharge." Contact Factory for additonal information regarding this option. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met.
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Figure 15: 184-Pin DIMM Dimensions
FRONT VIEW
5.256 (133.50) 5.244 (133.20) 0.125 (3.18) MAX
0.079 (2.00) R (4X)
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10 1.255 (31.88) 1.245 (31.62)
0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.035 (0.90) R
0.700 (17.78) TYP.
PIN 1
0.091 (2.30) TYP. 0.050 (1.27) TYP. 0.040 (1.02) TYP.
0.250 (6.35) TYP.
PIN 92
0.054 (1.37) 0.046 (1.17)
4.750 (120.65)
BACK VIEW
NO COMPONENTS THIS SIDE
PIN 184
1.95 (49.53)
0.150 (3.80) 2.55 (64.77)
PIN 93
0.150 (3.80) 0.394 (10.00) TYP. TYP.
NOTE:
All dimensions in inches (millimeters)
MAX or typical where noted. MIN
Data Sheet Designation
Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.. (c)2003 Micron Technology, Inc
128MB, 256MB (x72, ECC) 184-Pin DDR SDRAM DIMM
Revision History
Rev. B, Released, 2/03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/03 * Added Low Power option * Added -335 and -262 speed grades * Updated Idd, Capacitance, DC Electrical values * Added Pf-free option * Updated format Rev. A, Released, 01/02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 01/02 * New data sheet
09005aef808f8ccd DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.

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